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2019

A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers
J. Lagos, B. Hershberg, E. Martens, P. Wambacq, and J. Craninckx
In IEEE Journal of Solid-State Circuits, March, 2019.
»   [Paper]     [DOI]     [Bibtex]

@ARTICLE{2019-jssc-sp02-ringamp,
author={J. Lagos and B. Hershberg and E. Martens and P. Wambacq and J. Craninckx},
journal={{IEEE Journal of Solid-State Circuits}},
title={{A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers}},
year={2019},
volume={54},
number={3},
pages={646-658},
keywords={Gain;Linearity;Voltage measurement;Calibration;Voltage control;Transconductance;Resistance;Bias enhancement;gain boosting;pipelined ADC;ring amplifier;ringamp;single-channel},
doi={10.1109/JSSC.2018.2889680},
ISSN={0018-9200},
month={March},
type={journal}}

A 3.2GS/s 10 ENOB 61mW Ringamp ADC in 16nm with Background Monitoring of Distortion
B. Hershberg, D. Dermit, B. v. Liempd, E. Martens, N. Markulic, J. Lagos, and J. Craninckx
In 2019 IEEE International Solid- State Circuits Conference – (ISSCC), Feb, 2019.
»   [Paper]     [Slides]     [DOI]     [Bibtex]

@INPROCEEDINGS{2019-isscc-type1,
author={B. {Hershberg} and D. {Dermit} and B. v. {Liempd} and E. {Martens} and N. {Markulic} and J. {Lagos} and J. {Craninckx}},
booktitle={{2019 IEEE International Solid- State Circuits Conference - (ISSCC)}},
title={{A 3.2GS/s 10 ENOB 61mW Ringamp ADC in 16nm with Background Monitoring of Distortion}},
year={2019},
volume={},
number={},
pages={58-60},
keywords={Estimation;Monitoring;Distortion;Pipelines;Capacitors;Bandwidth;Hardware},
doi={10.1109/ISSCC.2019.8662290},
ISSN={2376-8606},
month={Feb},
type={conference}}

A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm
B. Hershberg, B. v. Liempd, N. Markulic, J. Lagos, E. Martens, D. Dermit, and J. Craninckx
In 2019 IEEE International Solid- State Circuits Conference – (ISSCC), Feb, 2019.
»   [Paper]     [Slides]     [DOI]     [Bibtex]

@INPROCEEDINGS{2019-isscc-type2,
author={B. {Hershberg} and B. v. {Liempd} and N. {Markulic} and J. {Lagos} and E. {Martens} and D. {Dermit} and J. {Craninckx}},
booktitle={{2019 IEEE International Solid- State Circuits Conference - (ISSCC)}},
title={{A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm}},
year={2019},
volume={},
number={},
pages={68-70},
keywords={Clocks;Timing;Pipelines;Quantization (signal);System recovery;Jitter;Protocols},
doi={10.1109/ISSCC.2019.8662319},
ISSN={2376-8606},
month={Feb},
type={conference}}

A Single-Channel, 600-MS/s, 12-b, Ringamp-Based Pipelined ADC in 28-nm CMOS
J. Lagos, B. Hershberg, E. Martens, P. Wambacq, and J. Craninckx
In IEEE Journal of Solid-State Circuits, Feb, 2019.
»   [Paper]     [DOI]     [Bibtex]

@ARTICLE{2019-jssc-sp01-ringamp,
author={J. {Lagos} and B. {Hershberg} and E. {Martens} and P. {Wambacq} and J. {Craninckx}},
journal={{IEEE Journal of Solid-State Circuits}},
title={{A Single-Channel, 600-MS/s, 12-b, Ringamp-Based Pipelined ADC in 28-nm CMOS}},
year={2019},
volume={54},
number={2},
pages={403-416},
keywords={amplifiers;analogue-digital conversion;calibration;circuit feedback;CMOS digital integrated circuits;integrated circuit design;low-power electronics;nanoelectronics;power-consuming analog circuits;intensive digital calibration;pipelined ADC;ring amplifier;low-voltage nanoscale CMOS designs;anti-parallel arrangement;CMOS transistors;single-channel prototype ADC;low-voltage operation;limited intrinsic gain;constant open-loop gain;deep nanoscale CMOS process;active ring amp-based common-mode feedback;tunable ring amp biasing scheme;output voltage characteristic;single-channel ring amp-based pipelined ADC;ADC design;Schreier figure-of-merit;Walden figure-of-merit;power 14.5 mW;size 28 nm;voltage 0.9 V;V;Linearity;Resistance;Calibration;Transistors;Resistors;Inverters;Gain;Active common-mode feedback (CMFB);gain calibration;pipelined ADC;ring amplifier (ringamp);single channel},
doi={10.1109/JSSC.2018.2879923},
ISSN={0018-9200},
month={Feb},
type={journal}}

2018

Wide-tuning range programmable threshold comparator using capacitive source-voltage shifting
E. Martens, B. Hershberg, and J. Craninckx
In Electronics Letters, December, 2018.
»   [Paper]     [DOI]     [Bibtex]

@ARTICLE{2018-eletters-ss-comparator,
author={E. Martens and B. Hershberg and J. Craninckx},
journal={{Electronics Letters}},
title={{Wide-tuning range programmable threshold comparator using capacitive source-voltage shifting}},
year={2018},
volume={54},
number={25},
pages={1417-1418},
keywords={CMOS digital integrated circuits;comparators (circuits);integrated circuit design;programmable circuits;transistor circuits;low decision delay;CMOS technology;programmable threshold;initial source voltages;capacitive source-voltage shifting;wide-tuning range programmable threshold comparator;transistor-level implementation;wide programmable tuning range;power-efficient comparator structure;tunable capacitance;source-voltage shifting;input transistors;comparator circuit;voltage 0.8 V;size 16.0 nm},
doi={10.1049/el.2018.6121},
ISSN={0013-5194},
month={December},
type={journal}}

A 1Gsps, 12-bit, single-channel pipelined ADC with dead-zone-degenerated ring amplifiers
J. Lagos, B. Hershberg, E. Martens, P. Wambacq, and J. Craninckx
In 2018 IEEE Custom Integrated Circuits Conference (CICC), April, 2018.
»   [Paper]     [DOI]     [Bibtex]

@INPROCEEDINGS{2018-cicc-ringamp,
author={J. Lagos and B. Hershberg and E. Martens and P. Wambacq and J. Craninckx},
booktitle={{2018 IEEE Custom Integrated Circuits Conference (CICC)}},
title={{A 1Gsps, 12-bit, single-channel pipelined ADC with dead-zone-degenerated ring amplifiers}},
year={2018},
volume={},
number={},
pages={1-4},
keywords={Bandwidth;Calibration;Clocks;Frequency measurement;Linearity;Pipelines;Semiconductor device measurement;Pipelined ADC;dead-zone degeneration;gain calibration;ring amplifier;ringamp;single-channel},
doi={10.1109/CICC.2018.8357056},
ISSN={},
month={April},
type={conference}}

A 69-dB SNDR 300-MS/s Two-Time Interleaved Pipelined SAR ADC in 16-nm CMOS FinFET With Capacitive Reference Stabilization
E. Martens, B. Hershberg, and J. Craninckx
In IEEE Journal of Solid-State Circuits, April, 2018.
»   [Paper]     [DOI]     [Bibtex]

@ARTICLE{2018-jssc-capacitive-reference-stabilization,
author={E. Martens and B. Hershberg and J. Craninckx},
journal={{IEEE Journal of Solid-State Circuits}},
title={{A 69-dB SNDR 300-MS/s Two-Time Interleaved Pipelined SAR ADC in 16-nm CMOS FinFET With Capacitive Reference Stabilization}},
year={2018},
volume={53},
number={4},
pages={1161-1171},
keywords={CMOS digital integrated circuits;analogue-digital conversion;circuit stability;digital-analogue conversion;harmonic distortion;CMOS FinFET;DAC switching;auxiliary DACs;capacitive reference stabilization;harmonic distortion;power 3.6 mW;reference decoupling capacitance;reference node;signal-dependent voltage ripple cancellation;size 16 nm;stabilization scheme;two-time interleaved pipelined SAR ADC;word length 11.2 bit;Calibration;Capacitance;Capacitors;FinFETs;Harmonic distortion;Reservoirs;Switches;ADC;FinFET technology;pipelined SAR ADC;reference pre-charging;reference ripple;reference stabilization},
doi={10.1109/JSSC.2017.2784762},
ISSN={0018-9200},
month={April},
type={journal}}

2017

A single-channel, 600Msps, 12bit, ringamp-based pipelined ADC in 28nm CMOS
J. Lagos, B. Hershberg, E. Martens, P. Wambacq, and J. Craninckx
In 2017 Symposium on VLSI Circuits, June, 2017.
»   [Paper]     [DOI]     [Bibtex]

@INPROCEEDINGS{2017-vlsi-ringamp,
author={J. Lagos and B. Hershberg and E. Martens and P. Wambacq and J. Craninckx},
booktitle={{2017 Symposium on VLSI Circuits}},
title={{A single-channel, 600Msps, 12bit, ringamp-based pipelined ADC in 28nm CMOS}},
year={2017},
pages={C96-C97},
keywords={Architecture;Bandwidth;Linearity;Nanoscale devices;Resistors;Robustness;Steady-state},
doi={10.23919/VLSIC.2017.8008561},
month={June},
type={conference}}

A 16nm 69dB SNDR 300MSps ADC with capacitive reference stabilization
E. Martens, B. Hershberg, and J. Craninckx
In 2017 Symposium on VLSI Circuits, June, 2017.
»   [Paper]     [DOI]     [Bibtex]

@INPROCEEDINGS{2017-vlsi-capacitive-reference-stabilization,
author={E. Martens and B. Hershberg and J. Craninckx},
booktitle={{2017 Symposium on VLSI Circuits}},
title={{A 16nm 69dB SNDR 300MSps ADC with capacitive reference stabilization}},
year={2017},
pages={C92-C93},
keywords={Calibration;Clocks;Gain;Harmonic analysis;Linearity;Switches;Table lookup},
doi={10.23919/VLSIC.2017.8008559},
month={June},
type={conference}}

2016

An integrated tunable electrical-balance filter with >60dB stopband attenuation and 1.75-3.7GHz stopband tuning range
B. van Liempd, B. Hershberg, P. Wambacq, and J. Craninckx
In 2016 11th European Microwave Integrated Circuits Conference (EuMIC), Oct, 2016.
»   [Paper]     [DOI]     [Bibtex]

@INPROCEEDINGS{2016-eumc-splitting-cap-ebd,
author={B. van Liempd and B. Hershberg and P. Wambacq and J. Craninckx},
booktitle={{2016 11th European Microwave Integrated Circuits Conference (EuMIC)}},
title={{An integrated tunable electrical-balance filter with >60dB stopband attenuation and 1.75-3.7GHz stopband tuning range}},
year={2016},
pages={500-503},
keywords={CMOS integrated circuits;MMIC;Q-factor;UHF filters;UHF integrated circuits;band-pass filters;band-stop filters;elemental semiconductors;low-pass filters;microwave filters;silicon-on-insulator;Si;frequency 1.75 GHz to 3.7 GHz;size 0.18 mum;Attenuation;Low-pass filters;Passband;Radio frequency;Resonant frequency;Resonator filters;Tuning;Electrical-balance;RF;filter;high attenuation;impedance-basedfiltering;low-loss;tunable filter},
doi={10.1109/EuMIC.2016.7777601},
month={Oct},
type={conference}}

A Dual-Frequency 0.7-to-1GHz Balance Network for Electrical Balance Duplexers
B. Hershberg, B. van Liempd, X. Zhang, P. Wambacq, and J. Craninckx
In 2016 IEEE International Solid-State Circuits Conference (ISSCC), Jan, 2016.
»   [Paper]     [Slides]     [DOI]     [Bibtex]

@INPROCEEDINGS{2016-isscc-dual-frequency-balance-network,
author={B. Hershberg and B. van Liempd and X. Zhang and P. Wambacq and J. Craninckx},
booktitle={{2016 IEEE International Solid-State Circuits Conference (ISSCC)}},
title={{A Dual-Frequency 0.7-to-1GHz Balance Network for Electrical Balance Duplexers}},
year={2016},
pages={356-357},
keywords={Antennas;Bandwidth;CMOS integrated circuits;Filtering;Impedance;Mathematical model;Tuning},
doi={10.1109/ISSCC.2016.7418054},
month={Jan},
type={conference},}

A Self-Calibrated 10Mb/s Phase Modulator with -37.4dB EVM Based on a 10.1-to-12.4GHz, -246.6dB-FOM, Fractional-N Subsampling PLL
N. Markulic, K. Raczkowski, E. Martens, P. E. P. Filho, B. Hershberg, P. Wambacq, and J. Craninckx
In 2016 IEEE International Solid-State Circuits Conference (ISSCC), Jan, 2016.
»   [Paper]     [DOI]     [Bibtex]

@INPROCEEDINGS{2016-isscc-fracn-sspll,
author={N. Markulic and K. Raczkowski and E. Martens and P. E. P. Filho and B. Hershberg and P. Wambacq and J. Craninckx},
booktitle={{2016 IEEE International Solid-State Circuits Conference (ISSCC)}},
title={{A Self-Calibrated 10Mb/s Phase Modulator with -37.4dB EVM Based on a 10.1-to-12.4GHz, -246.6dB-FOM, Fractional-N Subsampling PLL}},
year={2016},
pages={176-177},
keywords={Calibration;Phase locked loops;Phase modulation;Solid state circuits;Table lookup;Voltage-controlled oscillators},
doi={10.1109/ISSCC.2016.7417964},
month={Jan},
type={conference},}

A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation
N. Markulic, K. Raczkowski, E. Martens, P. P. E. Filho, B. Hershberg, P. Wambacq, and J. Craninckx
In IEEE Journal of Solid-State Circuits, Dec, 2016.
»   [Paper]     [DOI]     [Bibtex]

@ARTICLE{2016-jssc-fnsspll-2pmod,
author={N. Markulic and K. Raczkowski and E. Martens and P. E. Paro Filho and B. Hershberg and P. Wambacq and J. Craninckx},
journal={{IEEE Journal of Solid-State Circuits}},
title={{A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation}},
year={2016},
volume={51},
number={12},
pages={3078-3092},
keywords={digital-analogue conversion;minimum shift keying;phase locked loops;phase modulation;voltage-controlled oscillators;DTC gain;DTC nonlinearity;DTC-based analog subsampling PLL;VCO bank gain modulation;bit rate 10 Mbit/s;digital-to-time converter;nanoscale CMOS;phase modulators;self-calibrated fractional-N synthesis;two-point GMSK modulation;two-point modulation;Phase locked loops;Phase modulation;Quantization (signal);Voltage-controlled oscillators;Wideband;Analog PLL;GMSK;PLL;background calibration;digital-to-time converter (DTC);divider-less;fractional-N subsampling PLL (FNSSPLL);frequency synthesis;linearization;low jitter;phase/frequency modulation;polar modulation;subsampling PLL (SSPLL);two-point modulation;wideband modulation},
doi={10.1109/JSSC.2016.2596766},
ISSN={0018-9200},
month={Dec},
type={journal}}

A >70-dBm IIP3 Electrical-Balance Duplexer for Highly Integrated Tunable Front-Ends
B. van Liempd, B. Hershberg, S. Ariumi, K. Raczkowski, K. F. Bink, U. Karthaus, E. Martens, P. Wambacq, and J. Craninckx
In IEEE Transactions on Microwave Theory and Techniques, Dec, 2016.
»   [Paper]     [DOI]     [Bibtex]

@ARTICLE{2016-tmtt-ebd,
author={B. van Liempd and B. Hershberg and S. Ariumi and K. Raczkowski and K. F. Bink and U. Karthaus and E. Martens and P. Wambacq and J. Craninckx},
journal={{IEEE Transactions on Microwave Theory and Techniques}},
title={{A >70-dBm IIP3 Electrical-Balance Duplexer for Highly Integrated Tunable Front-Ends}},
year={2016},
volume={64},
number={12},
pages={4274-4286},
keywords={CMOS integrated circuits;differential amplifiers;low noise amplifiers;radiofrequency integrated circuits;silicon-on-insulator;IIP3 electrical-balance duplexer;RF silicon-on-insulator CMOS;antennas;differential low-noise amplifier;frequency 1.9 GHz to 2.2 GHz;highly integrated tunable front-ends;impedance balancing;insertion loss;linear switched capacitors;receiver;state-of-the-art linearity;transmitter;voltage standing wave ratio;Antennas;Distortion;Finite element analysis;Impedance;Jamming;Linearity;Radio frequency;CMOS integrated circuits;duplexer;electrical-balance (EB);frequency-division duplexing (FDD);hybrid transformer;linearity;silicon-on-insulator (SOI);tunable capacitors},
doi={10.1109/TMTT.2016.2613039},
ISSN={0018-9480},
month={Dec},
type={journal}}

2015

Real-time RF self-interference cancellation for in-band full duplex
T. Vermeulen, B. van Liempd, B. Hershberg, and S. Pollin
In Dynamic Spectrum Access Networks (DySPAN), 2015 IEEE International Symposium on, Sept, 2015.
»   [Paper]     [DOI]     [Abstract]     [Bibtex]

We demonstrate a real-time RF self-interference cancellation scheme for in-band full duplex using an electrical balance duplexer. The balance network in the duplexer has four 8-bit tunable capacitor banks, creating a four dimensional optimization space with over 4 billion settings. We present a particle swarm optimizer that is able to find a close to optimal solution within 1 ms. The goal of this demo is to show a self-interference cancellation scheme for very dynamic environments. More specifically our demo is able to mitigate instantaneous changes in the antenna impedance in order to keep the self-interference below the threshold.
@INPROCEEDINGS{2015-dyspan-ibfd,
author={Vermeulen, Tom and van Liempd, Barend and Hershberg, Benjamin and Pollin, Sofie},
booktitle={{Dynamic Spectrum Access Networks (DySPAN), 2015 IEEE International Symposium on}},
title={{Real-time RF self-interference cancellation for in-band full duplex}},
year={2015},
pages={275-276},
abstract={We demonstrate a real-time RF self-interference cancellation scheme for in-band full duplex using an electrical balance duplexer. The balance network in the duplexer has four 8-bit tunable capacitor banks, creating a four dimensional optimization space with over 4 billion settings. We present a particle swarm optimizer that is able to find a close to optimal solution within 1 ms. The goal of this demo is to show a self-interference cancellation scheme for very dynamic environments. More specifically our demo is able to mitigate instantaneous changes in the antenna impedance in order to keep the self-interference below the threshold.},
keywords={Antennas;Capacitors;Impedance;Optimization;Particle swarm optimization;Radio frequency;Real-time systems},
doi={10.1109/DySPAN.2015.7343915},
month={Sept},
type={conference}}

In-band full-duplex transceiver technology for 5G mobile networks
B. Debaillie, B. van Liempd, B. Hershberg, J. Craninckx, K. Rikkinen, D. J. van den Broek, E. A. M. Klumperink, and B. Nauta
In European Solid-State Circuits Conference (ESSCIRC), ESSCIRC 2015 – 41st, Sept, 2015.
»   [Paper]     [DOI]     [Abstract]     [Bibtex]

In-band full-duplex is a promising air interface technique to tackle several of the key challenges of next generation (5G) mobile networks. Simultaneous transmission and reception in the same frequency band increases the throughput and spectral efficiency, and reduces the air interface delay. Its implementation in 5G systems, however, restrains the full-duplex transceiver design requirements. Two analog integrated circuit solutions are presented and evaluated in the frame of 5G applications. The first design is a self-interference cancelling front-end implemented in 65nm CMOS, and the second design is an electrical-balance duplexer implemented in 0.18μm RF SOI CMOS. Both designs are attractive in the context of 5G; they allow dense integration, are configurable to support alternative and legacy standards, are compatible with conventional antenna(s), and they provide an attractive full-duplex performance for wireless communications.
@INPROCEEDINGS{2015-esscirc-ibfd,
author={Debaillie, B. and van Liempd, B. and Hershberg, B. and Craninckx, J. and Rikkinen, K. and van den Broek, D.J. and Klumperink, E.A.M. and Nauta, B.},
booktitle={{European Solid-State Circuits Conference (ESSCIRC), ESSCIRC 2015 - 41st}},
title={{In-band full-duplex transceiver technology for 5G mobile networks}},
year={2015},
pages={84-87},
abstract={In-band full-duplex is a promising air interface technique to tackle several of the key challenges of next generation (5G) mobile networks. Simultaneous transmission and reception in the same frequency band increases the throughput and spectral efficiency, and reduces the air interface delay. Its implementation in 5G systems, however, restrains the full-duplex transceiver design requirements. Two analog integrated circuit solutions are presented and evaluated in the frame of 5G applications. The first design is a self-interference cancelling front-end implemented in 65nm CMOS, and the second design is an electrical-balance duplexer implemented in 0.18μm RF SOI CMOS. Both designs are attractive in the context of 5G; they allow dense integration, are configurable to support alternative and legacy standards, are compatible with conventional antenna(s), and they provide an attractive full-duplex performance for wireless communications.},
keywords={5G mobile communication;CMOS integrated circuits;analogue integrated circuits;antennas;interference suppression;multiplexing equipment;next generation networks;radio transceivers;radiofrequency integrated circuits;silicon-on-insulator;5G mobile networks;RF SOI CMOS;Si;analog integrated circuit;conventional antenna;dense integration;electrical-balance duplexer;in-band full-duplex transceiver technology;next generation mobile networks;self-interference cancelling front-end;size 0.18 mum;size 65 nm;5G mobile communication;Antennas;Radio frequency;Silicon;Transceivers;Wireless communication;5G;In-band full-duplex;RF-IC;analog/RF cancellation;integrated circuits;self-interference},
doi={10.1109/ESSCIRC.2015.7313834},
ISSN={1930-8833},
month={Sept},
type={conference}}

An electrical-balance duplexer for in-band full-duplex with <-85dBm in-band distortion at +10dBm TX-power
B. van Liempd, B. Hershberg, B. Debaillie, P. Wambacq, and J. Craninckx
In European Solid-State Circuits Conference (ESSCIRC), ESSCIRC 2015 – 41st, Sept, 2015.
»   [Paper]     [DOI]     [Abstract]     [Bibtex]

When using electrical-balance duplexers (EBDs) to provide RF self-interference cancellation for in-band full-duplex, in-band distortion produced by nonlinear CMOS switches in the duplexer cause distortion that limits the headroom for additional self-interference cancellation in subsequent cancellation schemes in the transceiver. A prototype EBD is fabricated in 0.18μm SOI CMOS to investigate the dynamic range limitations of a transceiver architecture for next-generation wireless systems that supports in-band full-duplex and legacy FDD. Measurements show -85dBm in-band distortion at +10dBm TX input power, enough for short-range links at 10MHz BW.
@INPROCEEDINGS{2015-esscirc-ebd,
author={van Liempd, B. and Hershberg, B. and Debaillie, B. and Wambacq, P. and Craninckx, J.},
booktitle={{European Solid-State Circuits Conference (ESSCIRC), ESSCIRC 2015 - 41st}},
title={{An electrical-balance duplexer for in-band full-duplex with <-85dBm in-band distortion at +10dBm TX-power}}, year={2015}, pages={176-179}, abstract={When using electrical-balance duplexers (EBDs) to provide RF self-interference cancellation for in-band full-duplex, in-band distortion produced by nonlinear CMOS switches in the duplexer cause distortion that limits the headroom for additional self-interference cancellation in subsequent cancellation schemes in the transceiver. A prototype EBD is fabricated in 0.18μm SOI CMOS to investigate the dynamic range limitations of a transceiver architecture for next-generation wireless systems that supports in-band full-duplex and legacy FDD. Measurements show -85dBm in-band distortion at +10dBm TX input power, enough for short-range links at 10MHz BW.}, keywords={CMOS integrated circuits;frequency division multiplexing;interference suppression;multiplexing equipment;RF self-interference cancellation;SOI CMOS;bandwidth 10 MHz;dynamic range limitations;electrical-balance duplexers;in-band distortion;in-band full-duplex FDD;legacy FDD;next-generation wireless systems;nonlinear CMOS switches;prototype EBD;size 0.18 mum;transceiver architecture;Antenna measurements;Antennas;Distortion;Distortion measurement;Radio frequency;Silicon;Silicon carbide;In-band full-duplex;cancellation;electrical-balance duplexer;multi-tone test;self-interference}, doi={10.1109/ESSCIRC.2015.7313857}, ISSN={1930-8833}, month={Sept}, type={conference}}

A 9.2-12.7 GHz Wideband Fractional-N Subsampling PLL in 28 nm CMOS With 280 fs RMS Jitter
K. Raczkowski, N. Markulic, B. Hershberg, and J. Craninckx
In Solid-State Circuits, IEEE Journal of, March, 2015.
»   [Paper]     [DOI]     [Abstract]     [Bibtex]

This paper describes a fractional-N subsampling PLL in 28 nm CMOS. Fractional phase lock is made possible with almost no penalty in phase noise performance thanks to the use of a 10 bit, 0.55 ps/LSB digital-to-time converter (DTC) circuit operating on the sampling clock. The performance limitations of a practical DTC implementation are considered, and techniques for minimizing these limitations are presented. For example, background calibration guarantees appropriate DTC gain, reducing spurs. Operating at 10 GHz the system achieves −38 dBc of integrated phase noise (280 fs RMS jitter) when a worst case fractional spur of −43 dBc is present. In-band phase noise is at the level of −104 dBc/Hz. The class-B VCO can be tuned from 9.2 GHz to 12.7 GHz (32%). The total power consumption of the synthesizer, including the VCO, is 13 mW from 0.9 V and 1.8 V supplies.
@ARTICLE{2015-jssc-subsampling-pll,
author={Raczkowski, K. and Markulic, N. and Hershberg, B. and Craninckx, J.},
journal={{Solid-State Circuits, IEEE Journal of}},
title={{A 9.2-12.7 GHz Wideband Fractional-N Subsampling PLL in 28 nm CMOS With 280 fs RMS Jitter}},
year={2015},
month={March},
volume={PP},
number={99},
pages={1-11},
abstract={This paper describes a fractional-N subsampling PLL in 28 nm CMOS. Fractional phase lock is made possible with almost no penalty in phase noise performance thanks to the use of a 10 bit, 0.55 ps/LSB digital-to-time converter (DTC) circuit operating on the sampling clock. The performance limitations of a practical DTC implementation are considered, and techniques for minimizing these limitations are presented. For example, background calibration guarantees appropriate DTC gain, reducing spurs. Operating at 10 GHz the system achieves −38 dBc of integrated phase noise (280 fs RMS jitter) when a worst case fractional spur of −43 dBc is present. In-band phase noise is at the level of −104 dBc/Hz. The class-B VCO can be tuned from 9.2 GHz to 12.7 GHz (32%). The total power consumption of the synthesizer, including the VCO, is 13 mW from 0.9 V and 1.8 V supplies.},
keywords={Delays;Phase locked loops;Phase modulation;Phase noise;Quantization (signal);Voltage-controlled oscillators;CMOS process;digital-controlled oscillators;digital-to-time converter;fractional-N;frequency synthesis;jitter;phase noise;phase-locked loops;radio transceivers;sampling;voltage-controlled oscillators},
doi={10.1109/JSSC.2015.2403373},
type={journal},
ISSN={0018-9200},}

A +70dBm IIP3 single-ended electrical-balance duplexer in 0.18um SOI CMOS
B. van Liempd, B. Hershberg, K. Raczkowski, S. Ariumi, U. Karthaus, K. Bink, and J. Craninckx
In Solid- State Circuits Conference - (ISSCC), 2015 IEEE International, Feb, 2015.
»   [Paper]     [DOI]     [Abstract]     [Bibtex]

The electrical-balance (EB) duplexer concept explored in [1-4] suggests a possible integrated multiband alternative to conventional fixed-frequency surface-acoustic-wave (SAW) duplexers. The basic principle of the EB duplexer is to balance the impedances seen at the ports of a hybrid transformer to suppress signal transfer from the TX to the RX through signal cancellation (Fig. 2.2.1). While the potential payoff is tantalizing, several challenges must still be solved before EB duplexers can become commercially viable. Specifically, the duplexer must provide high isolation and linearity in both the TX and RX bands across wide bandwidth (BW), with low insertion loss (IL), all in the presence of a real antenna whose impedance is constantly varying due to real-world user interaction. In this paper, we present a duplexer that significantly advances the state-of-the-art for two of these critical challenges: linearity and insertion loss.
@INPROCEEDINGS{2015-isscc-ebd,
author={van Liempd, Barend and Hershberg, Benjamin and Raczkowski, Kuba and Ariumi, Saneaki and Karthaus, Udo and Bink, Karl-Frederik and Craninckx, Jan},
booktitle={{Solid- State Circuits Conference - (ISSCC), 2015 IEEE International}},
title={{A +70dBm IIP3 single-ended electrical-balance duplexer in 0.18um SOI CMOS}},
year={2015},
month={Feb},
pages={1-3},
abstract={The electrical-balance (EB) duplexer concept explored in [1-4] suggests a possible integrated multiband alternative to conventional fixed-frequency surface-acoustic-wave (SAW) duplexers. The basic principle of the EB duplexer is to balance the impedances seen at the ports of a hybrid transformer to suppress signal transfer from the TX to the RX through signal cancellation (Fig. 2.2.1). While the potential payoff is tantalizing, several challenges must still be solved before EB duplexers can become commercially viable. Specifically, the duplexer must provide high isolation and linearity in both the TX and RX bands across wide bandwidth (BW), with low insertion loss (IL), all in the presence of a real antenna whose impedance is constantly varying due to real-world user interaction. In this paper, we present a duplexer that significantly advances the state-of-the-art for two of these critical challenges: linearity and insertion loss.},
keywords={Antenna measurements;Antennas;Capacitors;Impedance;Insertion loss;Linearity;Ports (Computers)},
doi={10.1109/ISSCC.2015.7062851},
type={conference},}

The Ring Amplifier: Scalable Amplification with Ring Oscillators
B. Hershberg and U. Moon
In High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing, 2015.
(Book chapter version of AACD 2014 Workshop)
»   [Paper]     [Bibtex]

@incollection{2015-aacdchapter-ringamp,
title={{The Ring Amplifier: Scalable Amplification with Ring Oscillators}},
author={Hershberg, Benjamin and Moon, Un-Ku},
booktitle={{High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing}},
pages={399--418},
year={2015},
publisher={Springer},
type={book chapter},
note={(Book chapter version of AACD 2014 Workshop)},
}

2014

A 9.1-12.7 GHz VCO in 28nm CMOS with a bottom-pinning bias technique for digital varactor stress reduction
B. Hershberg, K. Raczkowski, K. Vaesen, and J. Craninckx
In European Solid State Circuits Conference (ESSCIRC), ESSCIRC 2014 - 40th, Sept, 2014.
»   [Paper]     [Slides]     [DOI]     [Abstract]     [Bibtex]

A wide tuning range class-B VCO in 28nm CMOS targeted for software defined radio applications demonstrates a technique for minimizing device stress while simultaneously optimizing off-state Q in digitally switched tank capacitor cells. The proposed digital varactor structure can be implemented using only capacitors and NMOS transistors, resulting in a very compact layout. The VCO operates between 9.1 - 12.7 GHz, achieving a tuning range of 32% and phase noise of -163.2 dBc/Hz at 20 MHz offset referred to a 915 MHz carrier while consuming 9.5 mW for a FoM of -187 dBc/Hz.
@INPROCEEDINGS{2014-esscirc-bottom-pinning-vco,
author={Hershberg, B. and Raczkowski, K. and Vaesen, K. and Craninckx, J.},
booktitle={{European Solid State Circuits Conference (ESSCIRC), ESSCIRC 2014 - 40th}},
title={{A 9.1-12.7 GHz VCO in 28nm CMOS with a bottom-pinning bias technique for digital varactor stress reduction}},
year={2014},
month={Sept},
pages={83-86},
abstract={A wide tuning range class-B VCO in 28nm CMOS targeted for software defined radio applications demonstrates a technique for minimizing device stress while simultaneously optimizing off-state Q in digitally switched tank capacitor cells. The proposed digital varactor structure can be implemented using only capacitors and NMOS transistors, resulting in a very compact layout. The VCO operates between 9.1 - 12.7 GHz, achieving a tuning range of 32% and phase noise of -163.2 dBc/Hz at 20 MHz offset referred to a 915 MHz carrier while consuming 9.5 mW for a FoM of -187 dBc/Hz.},
keywords={CMOS analogue integrated circuits;MMIC oscillators;field effect MMIC;stress analysis;varactors;voltage-controlled oscillators;CMOS process;NMOS transistors;bottom-pinning bias technique;capacitors;device stress minimization;digital varactor stress reduction;digitally switched tank capacitor cells;frequency 9.1 GHz to 12.7 GHz;off-state Q optimization;phase noise;power 9.5 mW;size 28 nm;software defined radio;wide tuning range class-B VCO;CMOS integrated circuits;Stress;Transistors;Tuning;Varactors;Voltage-controlled oscillators},
doi={10.1109/ESSCIRC.2014.6942027},
ISSN={1930-8833},
type={conference},}

A 9.2-12.7 GHz wideband fractional-N subsampling PLL in 28nm CMOS with 280fs RMS jitter
K. Raczkowski, N. Markulic, B. Hershberg, J. Van Driessche, and J. Craninckx
In Radio Frequency Integrated Circuits Symposium, 2014 IEEE, June, 2014.
»   [Paper]     [DOI]     [Abstract]     [Bibtex]

This paper describes a fractional-N subsampling PLL in 28nm CMOS. Fractional lock is achieved by using a 10bit digital-to-time converter (DTC) that generates a delayed sampling clock with minimal impact on PLL performance. Background calibration guarantees appropriate DTC gain, reducing spurs. The system achieves -38 dBc of integrated phase noise (280fs RMS jitter) at 10GHz when a worst-case fractional spur of -43 dBc is present. In-band phase noise is at the level of -104 dBc/Hz. The class-B VCO used can be tuned from 9.2 GHz to 12.7 GHz (32%). The total power consumption of the synthesizer, including the VCO, is 13 mW from 0.9V and 1.8V supplies.
@INPROCEEDINGS{2014-rfic-subsampling-pll,
author={Raczkowski, K. and Markulic, N. and Hershberg, B. and Van Driessche, J. and Craninckx, J.},
booktitle={{Radio Frequency Integrated Circuits Symposium, 2014 IEEE}},
title={{A 9.2-12.7 GHz wideband fractional-N subsampling PLL in 28nm CMOS with 280fs RMS jitter}},
year={2014},
month={June},
pages={89-92},
abstract={This paper describes a fractional-N subsampling PLL in 28nm CMOS. Fractional lock is achieved by using a 10bit digital-to-time converter (DTC) that generates a delayed sampling clock with minimal impact on PLL performance. Background calibration guarantees appropriate DTC gain, reducing spurs. The system achieves -38 dBc of integrated phase noise (280fs RMS jitter) at 10GHz when a worst-case fractional spur of -43 dBc is present. In-band phase noise is at the level of -104 dBc/Hz. The class-B VCO used can be tuned from 9.2 GHz to 12.7 GHz (32%). The total power consumption of the synthesizer, including the VCO, is 13 mW from 0.9V and 1.8V supplies.},
keywords={CMOS integrated circuits;calibration;microwave integrated circuits;microwave oscillators;phase locked loops;voltage-controlled oscillators;CMOS;DTC;RMS jitter;background calibration;class-B VCO;digital-to-time converter;fractional lock;frequency 9.2 GHz to 12.7 GHz;in-band phase noise;power 13 mW;size 28 nm;time 280 fs;voltage 0.9 V;voltage 1.8 V;wideband fractional-N subsampling PLL;word length 10 bit;worst-case fractional spur;CMOS integrated circuits;Clocks;Delays;Jitter;Phase locked loops;Phase noise;Voltage-controlled oscillators;Phase locked loops;fractional-N;frequency synthesis;jitter;phase noise;sampling},
doi={10.1109/RFIC.2014.6851666},
ISSN={1529-2517},
type={conference},}

Digitally Synthesized Stochastic Flash ADC Using Only Standard Digital Cells
S. Weaver, B. Hershberg, and U. Moon
In Circuits and Systems I: Regular Papers, IEEE Transactions on, Jan, 2014.
»   [Paper]     [DOI]     [Abstract]     [Bibtex]

It is demonstrated in this paper that it is possible to synthesize a stochastic flash ADC entirely from Verilog code and a standard digital library. An analog comparator is introduced that is constructed from two cross-coupled 3-input digital NAND gates, and can be described in Verilog. The synthesized comparators have random, Gaussian offsets that are used as virtual voltage references to make a flash ADC. A piecewise-linear inverse Gaussian CDF function is used to correct the nonlinearity introduced by the Gaussian offset distribution. The prototype IC is fabricated in 90 nm CMOS and implements a 2047-comparator version of the proposed architecture. All components including the comparators, the ones adder, and the peicewise inverse Gaussian function are all implemented in Verilog. Conventional digital synthesis and place-and-route is then used to generate the physical layout, making this the first fully synthesized ADC. SNDR of 35.9 dB (without calibration) is achieved at 210 MSPS from the Verilog synthesized design.
@ARTICLE{2014-tcas1-stochastic-adc,
author={Weaver, S. and Hershberg, B. and Un-Ku Moon},
journal={{Circuits and Systems I: Regular Papers, IEEE Transactions on}},
title={{Digitally Synthesized Stochastic Flash ADC Using Only Standard Digital Cells}},
year={2014},
month={Jan},
volume={61},
number={1},
pages={84-91},
abstract={It is demonstrated in this paper that it is possible to synthesize a stochastic flash ADC entirely from Verilog code and a standard digital library. An analog comparator is introduced that is constructed from two cross-coupled 3-input digital NAND gates, and can be described in Verilog. The synthesized comparators have random, Gaussian offsets that are used as virtual voltage references to make a flash ADC. A piecewise-linear inverse Gaussian CDF function is used to correct the nonlinearity introduced by the Gaussian offset distribution. The prototype IC is fabricated in 90 nm CMOS and implements a 2047-comparator version of the proposed architecture. All components including the comparators, the ones adder, and the peicewise inverse Gaussian function are all implemented in Verilog. Conventional digital synthesis and place-and-route is then used to generate the physical layout, making this the first fully synthesized ADC. SNDR of 35.9 dB (without calibration) is achieved at 210 MSPS from the Verilog synthesized design.},
keywords={CMOS logic circuits;Gaussian distribution;analogue-digital conversion;comparators (circuits);hardware description languages;network synthesis;piecewise linear techniques;stochastic processes;CMOS;Gaussian offset distribution;Verilog code;analog comparator;cross coupled digital NAND gates;digitally synthesized stochastic flash ADC;physical layout;piecewise linear inverse Gaussian CDF function;size 90 nm;standard digital cells;standard digital library;synthesized comparators;three input digital NAND gates;virtual voltage references;Analog-digital conversion;circuit synthesis;stochastic systems},
doi={10.1109/TCSI.2013.2268571},
ISSN={1549-8328},
type={journal},}

The Ring Amplifier: Scalable Amplification with Ring Oscillators
B. Hershberg and U. Moon
In 23rd workshop on advances in analog circuit design, Apr, 2014.
»   [Slides]     [Bibtex]

@incollection{2014-aacd-ringamp,
title={{The Ring Amplifier: Scalable Amplification with Ring Oscillators}},
author={Hershberg, Benjamin and Moon, Un-Ku},
booktitle={23rd Workshop on Advances in Analog Circuit Design},
year={2014},
month={Apr},
type={workshop},
}

2013

Parallel gain enhancement technique for switched-capacitor circuits
H. Venkatram, B. Hershberg, T. Oh, M. Gande, K. Sobue, K. Hamashita, and U. Moon
In Custom Integrated Circuits Conference (CICC), 2013 IEEE, Sept, 2013.
»   [Paper]     [DOI]     [Abstract]     [Bibtex]

This paper presents a unified classification model for gain enhancement techniques used in the design of high performance amplifiers. A parallel gain enhancement technique is proposed for switched capacitor circuits which combine the best features of the existing gain enhancement techniques found in continuous-time and discrete-time amplifiers. This technique utilizes two dependent closed loop amplifiers to enhance the open loop DC gain of the main amplifier. This replicated parallel gain enhancement (RPGE) technique enables a very high DC gain amplifier with an improved harmonic distortion performance. A proof of concept pipeline ADC in a 0.18 um CMOS process using RPGE technique achieves 75 dB SNDR, 91 dB SFDR, -87 dB THD at 20 MS/s. The measured 13 bit DNL and INL is +0.75/-0.36 and +0.88/-0.92 LSB respectively. The ADC operates from a supply voltage of 1.3 V, consumes 5.9 mW, occupies 3.06 mm2 and achieves a figure of merit of 65 fJ/CS.
@INPROCEEDINGS{2013-cicc-parallel-gain-enhancement,
author={Venkatram, H. and Hershberg, B. and Taehwan Oh and Gande, M. and Sobue, K. and Hamashita, K. and Un-Ku Moon},
booktitle={{Custom Integrated Circuits Conference (CICC), 2013 IEEE}},
title={{Parallel gain enhancement technique for switched-capacitor circuits}},
year={2013},
month={Sept},
pages={1-4},
abstract={This paper presents a unified classification model for gain enhancement techniques used in the design of high performance amplifiers. A parallel gain enhancement technique is proposed for switched capacitor circuits which combine the best features of the existing gain enhancement techniques found in continuous-time and discrete-time amplifiers. This technique utilizes two dependent closed loop amplifiers to enhance the open loop DC gain of the main amplifier. This replicated parallel gain enhancement (RPGE) technique enables a very high DC gain amplifier with an improved harmonic distortion performance. A proof of concept pipeline ADC in a 0.18 um CMOS process using RPGE technique achieves 75 dB SNDR, 91 dB SFDR, -87 dB THD at 20 MS/s. The measured 13 bit DNL and INL is +0.75/-0.36 and +0.88/-0.92 LSB respectively. The ADC operates from a supply voltage of 1.3 V, consumes 5.9 mW, occupies 3.06 mm2 and achieves a figure of merit of 65 fJ/CS.},
keywords={CMOS analogue integrated circuits;amplifiers;harmonic distortion;switched capacitor networks;CMOS process;DC gain amplifier;RPGE technique;closed loop amplifiers;discrete-time amplifiers;harmonic distortion performance;noise figure 75 dB;open loop DC gain;pipeline ADC;power 5.9 mW;replicated parallel gain enhancement;size 0.18 mum;voltage 1.3 V;Bandwidth;Capacitors;Clocks;Gain;Moon;Pipelines;Switched capacitor circuits},
doi={10.1109/CICC.2013.6658439},
type={conference},}

A 75.9dB-SNDR 2.96mW 29fJ/conv-step ringamp-only pipelined ADC
B. Hershberg and U. Moon
In VLSI Circuits (VLSIC), 2013 Symposium on, June, 2013.
»   [Paper]     [Abstract]     [Bibtex]

A high resolution pipelined ADC that performs precision amplification using only ring amplifiers is presented. Several enabling techniques are introduced, namely parallelization via the use of Composite Ring Amplifier Blocks and a new ringamp topology designed for high-precision use. The 15b ADC achieves 75.9 dB SNDR and 91.4 dB SFDR at 1.2 V supply and 20 Msps conversion rate. Total power consumption is 2.96 mW, resulting in a Figure-of-Merit of 29 fJ/c-step.
@INPROCEEDINGS{2013-vlsi-composite-ringamp-block,
author={Hershberg, B. and Un-Ku Moon},
booktitle={{VLSI Circuits (VLSIC), 2013 Symposium on}},
title={{A 75.9dB-SNDR 2.96mW 29fJ/conv-step ringamp-only pipelined ADC}},
year={2013},
month={June},
pages={C94-C95},
abstract={A high resolution pipelined ADC that performs precision amplification using only ring amplifiers is presented. Several enabling techniques are introduced, namely parallelization via the use of Composite Ring Amplifier Blocks and a new ringamp topology designed for high-precision use. The 15b ADC achieves 75.9 dB SNDR and 91.4 dB SFDR at 1.2 V supply and 20 Msps conversion rate. Total power consumption is 2.96 mW, resulting in a Figure-of-Merit of 29 fJ/c-step.},
keywords={amplifiers;analogue-digital conversion;SFDR;SNDR;composite ring amplifier block;parallelization technique;pipelined ADC;power 2.96 mW;precision amplification;ringamp topology;voltage 1.2 V;Accuracy;Circuit stability;Inverters;Structural rings;Switched capacitor circuits;Switches;Very large scale integration},
type={conference},}

2012

The effect of correlated level shifting on noise performance in switched capacitor circuits
B. Hershberg, T. Musah, S. Weaver, and U. Moon
In Circuits and Systems (ISCAS), 2012 IEEE International Symposium on, May, 2012.
»   [Paper]     [Slides]     [DOI]     [Abstract]     [Bibtex]

The relation between opamp noise and the size of the level shifting capacitor in correlated level-shifting (CLS) architectures is explored. Analysis is performed for a Split-CLS switched capacitor amplification circuit, and many of the conclusions in this paper are applicable to more general CLS architectures as well. A theoretical model for noise is developed and shown to be in good agreement with simulation. It is found that for practical design values, the size of the level-shifting capacitor only weakly influences noise performance.
@INPROCEEDINGS{2012-iscas-cls-noise,
author={Hershberg, B. and Musah, T. and Weaver, S. and Un-Ku Moon},
booktitle={{Circuits and Systems (ISCAS), 2012 IEEE International Symposium on}},
title={{The effect of correlated level shifting on noise performance in switched capacitor circuits}},
year={2012},
month={May},
pages={942-945},
abstract={The relation between opamp noise and the size of the level shifting capacitor in correlated level-shifting (CLS) architectures is explored. Analysis is performed for a Split-CLS switched capacitor amplification circuit, and many of the conclusions in this paper are applicable to more general CLS architectures as well. A theoretical model for noise is developed and shown to be in good agreement with simulation. It is found that for practical design values, the size of the level-shifting capacitor only weakly influences noise performance.},
keywords={circuit noise;operational amplifiers;switched capacitor networks;correlated level shifting;general CLS architectures;level shifting capacitor;noise performance;opamp noise;split-CLS switched capacitor amplification circuit;switched capacitor circuits;Capacitance;Capacitors;Gain;Integrated circuit modeling;Noise;Transfer functions;Transistors},
doi={10.1109/ISCAS.2012.6272200},
ISSN={0271-4302},
type={conference},}

Ring Amplification for Switched Capacitor Circuits
B. Hershberg
PhD Thesis, Oregon State University , June, 2012.
»   [Paper]     [Bibtex]

@phdthesis{2012-phdthesis-hershberg,
title={{Ring Amplification for Switched Capacitor Circuits}},
author={Hershberg, Benjamin},
school={Oregon State University},
year={2012},
month={June},
address={Corvallis, OR, USA},
type={thesis},
}

A 61.5dB SNDR pipelined ADC using simple highly-scalable ring amplifiers
B. Hershberg, S. Weaver, K. Sobue, S. Takeuchi, K. Hamashita, and U. Moon
In VLSI Circuits (VLSIC), 2012 Symposium on, June, 2012.
»   [Paper]     [Slides]     [DOI]     [Abstract]     [Bibtex]

A ring amplifier based pipelined ADC is presented that uses simple cells constructed from small inverters and capacitors to perform amplification. The basic ring amplifier structure is characterized and demonstrated to be highly scalable, power efficient, and compression-immune (inherent rail-to-rail output swing). The prototype 10.5-bit ADC, fabricated in 0.18μm CMOS technology, achieves 61.5dB SNDR at a 30MHz sampling rate and consumes 2.6mW, resulting in a FoM of 90fJ/conversion-step.
@INPROCEEDINGS{2012-vlsi-ringamp,
author={Hershberg, B. and Weaver, S. and Sobue, K. and Takeuchi, S. and Hamashita, K. and Un-Ku Moon},
booktitle={{VLSI Circuits (VLSIC), 2012 Symposium on}},
title={{A 61.5dB SNDR pipelined ADC using simple highly-scalable ring amplifiers}},
year={2012},
month={June},
pages={32-33},
abstract={A ring amplifier based pipelined ADC is presented that uses simple cells constructed from small inverters and capacitors to perform amplification. The basic ring amplifier structure is characterized and demonstrated to be highly scalable, power efficient, and compression-immune (inherent rail-to-rail output swing). The prototype 10.5-bit ADC, fabricated in 0.18μm CMOS technology, achieves 61.5dB SNDR at a 30MHz sampling rate and consumes 2.6mW, resulting in a FoM of 90fJ/conversion-step.},
keywords={CMOS integrated circuits;amplifiers;analogue-digital conversion;10.5-bit ADC;CMOS technology;SNDR pipelined ADC;capacitor;compression-immune;frequency 30 MHz;inherent rail-to-rail output swing;noise figure 61.5 dB;power efficient;ring amplifier based pipelined ADC;ring amplifier structure;Accuracy;CMOS integrated circuits;CMOS technology;Digital audio players;Inverters;Structural rings;Transistors},
doi={10.1109/VLSIC.2012.6243775},
type={conference},}

Ring amplifiers for switched-capacitor circuits
B. Hershberg, S. Weaver, K. Sobue, S. Takeuchi, K. Hamashita, and U. Moon
In Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 IEEE International, Feb, 2012.
»   [Paper]     [Slides]     [DOI]     [Abstract]     [Bibtex]

To overcome the challenges that CMOS process scaling has imposed on the design of switched-capacitor amplification circuits, designers must consider a growing number of design tradeoffs and employ new circuit techniques in order to achieve required accuracies, often at a cost of added power and complexity. This amplification performance bottleneck has been highlighted in recent years by the disparity in achievable power efficiency between SAR ADCs versus ADC structures that require amplification [1]. In many analog and mixed-signal topics, a comparison like this doesn't even exist, simply because amplification is a necessity. Even SAR ADCs have their limitations, particularly at higher resolutions where matching and noise constraints begin to dominate capacitor sizing and comparator power requirements.
@INPROCEEDINGS{2012-isscc-ringamp,
author={Hershberg, B. and Weaver, S. and Sobue, K. and Takeuchi, S. and Hamashita, K. and Un-Ku Moon},
booktitle={{Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 IEEE International}},
title={{Ring amplifiers for switched-capacitor circuits}},
year={2012},
month={Feb},
pages={460-462},
abstract={To overcome the challenges that CMOS process scaling has imposed on the design of switched-capacitor amplification circuits, designers must consider a growing number of design tradeoffs and employ new circuit techniques in order to achieve required accuracies, often at a cost of added power and complexity. This amplification performance bottleneck has been highlighted in recent years by the disparity in achievable power efficiency between SAR ADCs versus ADC structures that require amplification [1]. In many analog and mixed-signal topics, a comparison like this doesn't even exist, simply because amplification is a necessity. Even SAR ADCs have their limitations, particularly at higher resolutions where matching and noise constraints begin to dominate capacitor sizing and comparator power requirements.},
keywords={CMOS integrated circuits;amplifiers;analogue-digital conversion;integrated circuit design;switched capacitor networks;CMOS process scaling;SAR ADC structure;amplification performance;capacitor sizing;comparator power requirement;power efficiency;ring amplifier;switched-capacitor amplification circuit;Accuracy;Capacitors;Pipelines;Ring oscillators;Solid state circuits;Switches},
doi={10.1109/ISSCC.2012.6177090},
ISSN={0193-6530},
type={conference},}

Ring Amplifiers for Switched Capacitor Circuits
B. Hershberg, S. Weaver, K. Sobue, S. Takeuchi, K. Hamashita, and U. Moon
In Solid-State Circuits, IEEE Journal of, Dec, 2012.
»   [Paper]     [DOI]     [Abstract]     [Bibtex]

In this paper the fundamental concept of ring amplification is introduced and explored. Ring amplifiers enable efficient amplification in scaled environments, and possess the benefits of efficient slew-based charging, rapid stabilization, compression-immunity (inherent rail-to-rail output swing), and performance that scales with process technology. A basic operational theory is established, and the core benefits of this technique are identified. Measured results from two separate ring amplifier based pipelined ADCs are presented. The first prototype IC, a simple 10.5-bit, 61.5 dB SNDR pipelined ADC which uses only ring amplifiers, is used to demonstrate the core benefits. The second fabricated IC presented is a high-resolution pipelined ADC which employs the technique of Split-CLS to perform efficient, accurate amplification aided by ring amplifiers. The 15-bit ADC is implemented in a 0.18 μm CMOS technology and achieves 76.8 dB SNDR and 95.4 dB SFDR at 20 Msps while consuming 5.1 mW, achieving a FoM of 45 fJ/conversion-step.
@ARTICLE{2012-jssc-ringamp,
author={Hershberg, B. and Weaver, S. and Sobue, K. and Takeuchi, S. and Hamashita, K. and Un-Ku Moon},
journal={{Solid-State Circuits, IEEE Journal of}},
title={{Ring Amplifiers for Switched Capacitor Circuits}},
year={2012},
month={Dec},
volume={47},
number={12},
pages={2928-2942},
abstract={In this paper the fundamental concept of ring amplification is introduced and explored. Ring amplifiers enable efficient amplification in scaled environments, and possess the benefits of efficient slew-based charging, rapid stabilization, compression-immunity (inherent rail-to-rail output swing), and performance that scales with process technology. A basic operational theory is established, and the core benefits of this technique are identified. Measured results from two separate ring amplifier based pipelined ADCs are presented. The first prototype IC, a simple 10.5-bit, 61.5 dB SNDR pipelined ADC which uses only ring amplifiers, is used to demonstrate the core benefits. The second fabricated IC presented is a high-resolution pipelined ADC which employs the technique of Split-CLS to perform efficient, accurate amplification aided by ring amplifiers. The 15-bit ADC is implemented in a 0.18 μm CMOS technology and achieves 76.8 dB SNDR and 95.4 dB SFDR at 20 Msps while consuming 5.1 mW, achieving a FoM of 45 fJ/conversion-step.},
keywords={CMOS analogue integrated circuits;amplifiers;analogue-digital conversion;CMOS technology;SNDR pipelined ADC;Split-CLS;compression-immunity;power 5.1 mW;rapid stabilization;ring amplification;ring amplifier;size 0.18 micron;slew-based charging;switched capacitor circuit;word length 10.5 bit;word length 15 bit;Accuracy;CMOS integrated circuits;Gain;Inverters;Ring oscillators;Stability analysis;Transistors;A/D;ADC;CLS;RAMP;analog to digital conversion;analog to digital converter;correlated level shifting;high resolution;low power;nanoscale CMOS;rail-to-rail;ring amp;ring amplification;ring amplifier;ringamp;scalability;scaling;slew-based;split-CLS;stabilized ring oscillator;switched capacitor},
doi={10.1109/JSSC.2012.2217865},
ISSN={0018-9200},
type={journal},}

2011

Domino-Logic-Based ADC for Digital Synthesis
S. Weaver, B. Hershberg, N. Maghari, and U. Moon
In Circuits and Systems II: Express Briefs, IEEE Transactions on, Nov, 2011.
»   [Paper]     [DOI]     [Abstract]     [Bibtex]

A low-power synthesizable analog-to-digital converter (ADC) is presented. By cascading many digital-like domino-logic cells whose propagation delay is influenced by an analog input voltage, a digital value is obtained at the end of the allowed ripple period by determining the number of cells that the ripple passed through. The sample-and-hold is simply a bootstrapped switch into a small sampling capacitor. As each domino-logic cell passes the ripple, charge is kicked back onto the input capacitor, which creates a significant second harmonic. Distortion caused by even harmonics is canceled by implementing a pseudodifferential structure. A test chip is fabricated in 0.18-μm CMOS. The test chip achieves over 5.4-bit effective number of bits up to 50 MS/s with a 1.3-V supply. With a sampling frequency of 50 MS/s and a 24-MHz input, a 34.2-dB signal-to-noise-plus distortion ratio is achieved while consuming 433 μW and occupying only 0.094 mm2.
@ARTICLE{2011-tcas2-domino-logic,
author={Weaver, S. and Hershberg, B. and Maghari, N. and Un-Ku Moon},
journal={{Circuits and Systems II: Express Briefs, IEEE Transactions on}},
title={{Domino-Logic-Based ADC for Digital Synthesis}},
year={2011},
month={Nov},
volume={58},
number={11},
pages={744-747},
abstract={A low-power synthesizable analog-to-digital converter (ADC) is presented. By cascading many digital-like domino-logic cells whose propagation delay is influenced by an analog input voltage, a digital value is obtained at the end of the allowed ripple period by determining the number of cells that the ripple passed through. The sample-and-hold is simply a bootstrapped switch into a small sampling capacitor. As each domino-logic cell passes the ripple, charge is kicked back onto the input capacitor, which creates a significant second harmonic. Distortion caused by even harmonics is canceled by implementing a pseudodifferential structure. A test chip is fabricated in 0.18-μm CMOS. The test chip achieves over 5.4-bit effective number of bits up to 50 MS/s with a 1.3-V supply. With a sampling frequency of 50 MS/s and a 24-MHz input, a 34.2-dB signal-to-noise-plus distortion ratio is achieved while consuming 433 μW and occupying only 0.094 mm2.},
keywords={CMOS integrated circuits;analogue-digital conversion;low-power electronics;network synthesis;sample and hold circuits;CMOS;analog input voltage;bootstrapped switch;digital synthesis;digital value;digital-like domino-logic cells;domino-logic-based ADC;frequency 24 MHz;low-power synthesizable analog-to-digital converter;power 433 muW;propagation delay;pseudodifferential structure;sample-and-hold;sampling capacitor;signal-to-noise-plus distortion ratio;size 0.18 mum;voltage 1.3 V;word length 5.4 bit;Analog-digital conversion;CMOS integrated circuits;Harmonic analysis;Logic gates;Analog-digital conversion;low power;scaling;synthesis},
doi={10.1109/TCSII.2011.2168019},
ISSN={1549-7747},
type={journal},}

Binary Access Memory: An optimized lookup table for successive approximation applications
B. Hershberg, S. Weaver, S. Takeuchi, K. Hamashita, and U. Moon
In Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, May, 2011.
»   [Paper]     [Slides]     [DOI]     [Abstract]     [Bibtex]

An optimized memory structure, Binary Access Memory (BAM), is presented for successive approximation applications that employ an error correction lookup table. Unlike true random-access memory, the probability of different codes occurring in a binary successive approximation access pattern is not uniformly distributed. BAM exploits this fact in several ways to reduce the number of sub-block switches, the average and worst-case access latency, and power consumption compared to a conventional SRAM lookup table. A simple technique for using BAM in an asynchronous successive approximation design is also presented.
@INPROCEEDINGS{2011-iscas-binary-access-memory,
author={Hershberg, B. and Weaver, S. and Takeuchi, S. and Hamashita, K. and Un-Ku Moon},
booktitle={{Circuits and Systems (ISCAS), 2011 IEEE International Symposium on}},
title={{Binary Access Memory: An optimized lookup table for successive approximation applications}},
year={2011},
month={May},
pages={1620-1623},
abstract={An optimized memory structure, Binary Access Memory (BAM), is presented for successive approximation applications that employ an error correction lookup table. Unlike true random-access memory, the probability of different codes occurring in a binary successive approximation access pattern is not uniformly distributed. BAM exploits this fact in several ways to reduce the number of sub-block switches, the average and worst-case access latency, and power consumption compared to a conventional SRAM lookup table. A simple technique for using BAM in an asynchronous successive approximation design is also presented.},
keywords={SRAM chips;table lookup;access latency;asynchronous successive approximation design;binary access memory;error correction lookup table;sub-block switches;true random-access memory;Approximation methods;Binary trees;Calibration;Decoding;Error correction codes;Random access memory;Timing},
doi={10.1109/ISCAS.2011.5937889},
ISSN={0271-4302},
type={conference},}

Digitally synthesized stochastic flash ADC using only standard digital cells
S. Weaver, B. Hershberg, and U. Moon
In VLSI Circuits (VLSIC), 2011 Symposium on, June, 2011.
»   [Paper]     [Abstract]     [Bibtex]

An ADC is synthesized entirely from Verilog code in 90nm digital CMOS using a standard digital cell library. An analog comparator is generated by cross-coupling two 3-input NAND gates. The random comparator offsets are used as the ADC references and are Gaussian. An implicitly aligned three-section piecewise-linear inverse Gaussian CDF function on chip linearizes the output. SNDR of 35.9dB is achieved at 210MSPS.
@INPROCEEDINGS{2011-vlsi-stochastic-adc,
author={Weaver, S. and Hershberg, B. and Un-Ku Moon},
booktitle={{VLSI Circuits (VLSIC), 2011 Symposium on}},
title={{Digitally synthesized stochastic flash ADC using only standard digital cells}},
year={2011},
month={June},
pages={266-267},
abstract={An ADC is synthesized entirely from Verilog code in 90nm digital CMOS using a standard digital cell library. An analog comparator is generated by cross-coupling two 3-input NAND gates. The random comparator offsets are used as the ADC references and are Gaussian. An implicitly aligned three-section piecewise-linear inverse Gaussian CDF function on chip linearizes the output. SNDR of 35.9dB is achieved at 210MSPS.},
keywords={CMOS digital integrated circuits;Gaussian distribution;analogue-digital conversion;comparators (circuits);flash memories;logic gates;3-input NAND gates;Verilog code;analog comparator;digital CMOS;digital cell library;digitally synthesized stochastic flash ADC;size 90 nm;three-section piecewise-linear inverse Gaussian CDF function;Clocks;Digital signal processing;Frequency measurement;Hardware;Hardware design languages;MOS devices;Shape},
ISSN={2158-5601},
type={conference},}

2010

Stochastic Flash Analog-to-Digital Conversion
S. Weaver, B. Hershberg, P. Kurahashi, D. Knierim, and U. Moon
In Circuits and Systems I: Regular Papers, IEEE Transactions on, Nov, 2010.
»   [Paper]     [DOI]     [Abstract]     [Bibtex]

A stochastic flash analog-to-digital converter (ADC) is presented. A standard flash uses a resistor string to set individual comparator trip points. A stochastic flash ADC uses random comparator offset to set the trip points. Since the comparators are no longer sized for small offset, they can be shrunk down into digital cells. Using comparators that are implemented as digital cells produces a large variation of comparator offset. Typically, this is considered a disadvantage, but in our case, this large standard deviation of offset is used to set the input signal range. By designing an ADC that is made up entirely of digital cells, it is a natural candidate for a synthesizable ADC. Comparator trip points follow the nonlinear transfer function described by a Gaussian cumulative distribution function, and a technique is presented that reduces this nonlinearity by changing the overall transfer function of the stochastic flash ADC. A test chip is fabricated in 0.18- CMOS to demonstrate the concept.
@ARTICLE{2010-tcas1-stochastic-adc,
author={Weaver, S. and Hershberg, B. and Kurahashi, P. and Knierim, D. and Un-Ku Moon},
journal={{Circuits and Systems I: Regular Papers, IEEE Transactions on}},
title={{Stochastic Flash Analog-to-Digital Conversion}},
year={2010},
month={Nov},
volume={57},
number={11},
pages={2825-2833},
abstract={A stochastic flash analog-to-digital converter (ADC) is presented. A standard flash uses a resistor string to set individual comparator trip points. A stochastic flash ADC uses random comparator offset to set the trip points. Since the comparators are no longer sized for small offset, they can be shrunk down into digital cells. Using comparators that are implemented as digital cells produces a large variation of comparator offset. Typically, this is considered a disadvantage, but in our case, this large standard deviation of offset is used to set the input signal range. By designing an ADC that is made up entirely of digital cells, it is a natural candidate for a synthesizable ADC. Comparator trip points follow the nonlinear transfer function described by a Gaussian cumulative distribution function, and a technique is presented that reduces this nonlinearity by changing the overall transfer function of the stochastic flash ADC. A test chip is fabricated in 0.18- CMOS to demonstrate the concept.},
keywords={Gaussian distribution;analogue-digital conversion;comparators (circuits);Gaussian cumulative distribution function;comparator offset;comparator trip points;digital cell;nonlinear transfer function;resistor string;stochastic flash analog-to-digital conversion;Analog-digital conversion;Calibration;Costs;Distribution functions;Moon;Resistors;Signal synthesis;Stochastic processes;Transfer functions;Voltage;Analog–digital conversion;comparators;statistical analysis;stochastic systems},
doi={10.1109/TCSI.2010.2050225},
ISSN={1549-8328},
type={journal},}

A 1.4V signal swing hybrid CLS-opamp/ZCBC pipelined ADC using a 300mV output swing opamp
B. Hershberg, S. T. Weaver, and U. Moon
In Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International, Feb, 2010.
»   [Paper]     [Slides]     [DOI]     [Abstract]     [Bibtex]

A Hybrid CLS-opamp/ZCBC pipelined ADC is introduced to improve accuracy, robustness, and power efficiency. Fast and accurate residue amplification is achieved by invoking a short ZCBC operation followed by CLS-opamp settling. Measured ENOB is better than 11 b at sampling rate of 20 MHz.
@INPROCEEDINGS{2010-isscc-split-cls-zcbc,
author={Hershberg, B. and Weaver, S.T. and Un-Ku Moon},
booktitle={{Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International}},
title={{A 1.4V signal swing hybrid CLS-opamp/ZCBC pipelined ADC using a 300mV output swing opamp}},
year={2010},
month={Feb},
pages={302-303},
abstract={A Hybrid CLS-opamp/ZCBC pipelined ADC is introduced to improve accuracy, robustness, and power efficiency. Fast and accurate residue amplification is achieved by invoking a short ZCBC operation followed by CLS-opamp settling. Measured ENOB is better than 11 b at sampling rate of 20 MHz.},
keywords={CMOS integrated circuits;analogue-digital conversion;operational amplifiers;pipeline arithmetic;ENOB;correlated level-shifting;frequency 20 MHz;residue amplification;signal swing hybrid CLS-Opamp-ZCBC pipelined ADC;voltage 1.4 V;voltage 300 mV;voltage output swing opamp;zero-crossing based circuits;CMOS technology;Pipelines;Robustness;Sampling methods;Switches;Tail;Temperature;Testing;Timing;Voltage},
doi={10.1109/ISSCC.2010.5433894},
ISSN={0193-6530},
type={conference},}

Asynchronous CLS for Zero Crossing based Circuits
H. Venkatram, B. Hershberg, and U. Moon
In Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on, Dec, 2010.
»   [Paper]     [DOI]     [Abstract]     [Bibtex]

This paper introduces Asynchronous correlated level shifting (ACLS) for Zero Crossing based Circuits. ACLS technique for Zero crossing based circuits provides rail-to-rail, asynchronous operation for the estimation and level shifting phase. The current source non-linearity is reduced and the power supply rejection ratio is improved.
@INPROCEEDINGS{2010-icecs-asynchronous-cls,
author={Venkatram, H. and Hershberg, B. and Un-Ku Moon},
booktitle={{Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on}},
title={{Asynchronous CLS for Zero Crossing based Circuits}},
year={2010},
month={Dec},
pages={1025-1028},
abstract={This paper introduces Asynchronous correlated level shifting (ACLS) for Zero Crossing based Circuits. ACLS technique for Zero crossing based circuits provides rail-to-rail, asynchronous operation for the estimation and level shifting phase. The current source non-linearity is reduced and the power supply rejection ratio is improved.},
keywords={operational amplifiers;ACLS technique;asynchronous CLS;asynchronous correlated level shifting;current source nonlinearity;level shifting phase;power supply rejection ratio;rail-to-rail asynchronous operation;zero crossing-based circuits;Capacitors;ACLS;Rail-to-Rail operation;ZCBC},
doi={10.1109/ICECS.2010.5724689},
type={conference},}

ENOB calculation for ADCs with input-correlated quantization error using a sine-wave test
S. Weaver, B. Hershberg, and U. Moon
In Microelectronics (ICM), 2010 International Conference on, Dec, 2010.
»   [Paper]     [DOI]     [Abstract]     [Bibtex]

The equation for calculating ENOB from SNDR of a sine-wave test is only accurate when noise is uncorrelated to the input. In this paper, the equation for calculating ENOB from SNDR is derived for an ideal and a uniform stochastic ADC. The result of these derivations shows that calculating ENOB from SNDR using the conventional equation causes a better-than-actual result in the case a uniform stochastic ADC.
@INPROCEEDINGS{2010-icm-enob-calculation-for-stochastic-adcs,
author={Weaver, S. and Hershberg, B. and Un-Ku Moon},
booktitle={{Microelectronics (ICM), 2010 International Conference on}},
title={{ENOB calculation for ADCs with input-correlated quantization error using a sine-wave test}},
year={2010},
month={Dec},
pages={5-8},
abstract={The equation for calculating ENOB from SNDR of a sine-wave test is only accurate when noise is uncorrelated to the input. In this paper, the equation for calculating ENOB from SNDR is derived for an ideal and a uniform stochastic ADC. The result of these derivations shows that calculating ENOB from SNDR using the conventional equation causes a better-than-actual result in the case a uniform stochastic ADC.},
keywords={analogue-digital conversion;ENOB calculation;input-correlated quantization error;sine-wave test;uniform stochastic ADC;Equations;Mathematical model;Probability density function;Quantization;Random variables;Signal to noise ratio},
doi={10.1109/ICM.2010.5696205},
type={conference},}

PDF folding for stochastic flash ADCs
S. Weaver, B. Hershberg, and U. Moon
In Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on, Dec, 2010.
»   [Paper]     [DOI]     [Abstract]     [Bibtex]

A circuit is presented that halves the number of comparators required for a two-group stochastic flash ADC. In a two-group stochastic flash ADC, two Gaussian PDFs are shifted left and right by applying a global offset reference to the two groups of comparators. This creates a virtual uniform distribution of comparator offset between the two global offsets. Over half of the comparators fall outside of the virtual uniform distribution and are not used. The proposed circuit inverts the polarity of each comparator offset until it is within the useful range, creating a virtual uniform distribution of comparator offsets with few comparators wasted.
@INPROCEEDINGS{2010-icecs-pdf-folding-stochastic-adc,
author={Weaver, S. and Hershberg, B. and Un-Ku Moon},
booktitle={{Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on}},
title={{PDF folding for stochastic flash ADCs}},
year={2010},
month={Dec},
pages={770-773},
abstract={A circuit is presented that halves the number of comparators required for a two-group stochastic flash ADC. In a two-group stochastic flash ADC, two Gaussian PDFs are shifted left and right by applying a global offset reference to the two groups of comparators. This creates a virtual uniform distribution of comparator offset between the two global offsets. Over half of the comparators fall outside of the virtual uniform distribution and are not used. The proposed circuit inverts the polarity of each comparator offset until it is within the useful range, creating a virtual uniform distribution of comparator offsets with few comparators wasted.},
keywords={Gaussian distribution;analogue-digital conversion;stochastic processes;Gaussian PDF;PDF folding;comparators;global offset reference;two-group stochastic flash ADC;virtual uniform distribution;Moon},
doi={10.1109/ICECS.2010.5724626},
type={conference},}

Design of a Split-CLS Pipelined ADC With Full Signal Swing Using an Accurate But Fractional Signal Swing Opamp
B. Hershberg, S. Weaver, and U. Moon
In Solid-State Circuits, IEEE Journal of, Dec, 2010.
»   [Paper]     [DOI]     [Abstract]     [Bibtex]

Building on the technique of correlated level shifting (CLS), Split-CLS is introduced as a viable way to enable the design of high performance, high resolution A/D converters in deep submicron CMOS processes. One possible implementation of Split-CLS is presented, which achieves very high effective gain, and combines the fast, high efficiency charging of a zero-crossing based circuit (ZCBC) with the high-accuracy, low power settling of a double-cascode telescopic opamp. A dynamic zero-crossing detector (ZCD) conserves power in the ZCBC by only creating high bandwidth in the ZCD near the zero-crossing instant. Measured results are presented from a pipelined A/D converter fabricated in 0.18 m CMOS. Using the Split-CLS structure, an opamp with 300 mV output swing is used to produce a pipeline stage output swing of 1.4 V. The proof-of-concept test chip achieves 68.3 dB SNDR (11.1b ENOB) and 76.3dB SFDR while sampling at 20 MHz, and consumes 17.2 mW at 1.8 V supply.
@ARTICLE{2010-jssc-split-cls-adc,
author={Hershberg, B. and Weaver, S. and Un-Ku Moon},
journal={{Solid-State Circuits, IEEE Journal of}},
title={{Design of a Split-CLS Pipelined ADC With Full Signal Swing Using an Accurate But Fractional Signal Swing Opamp}},
year={2010},
month={Dec},
volume={45},
number={12},
pages={2623-2633},
abstract={Building on the technique of correlated level shifting (CLS), Split-CLS is introduced as a viable way to enable the design of high performance, high resolution A/D converters in deep submicron CMOS processes. One possible implementation of Split-CLS is presented, which achieves very high effective gain, and combines the fast, high efficiency charging of a zero-crossing based circuit (ZCBC) with the high-accuracy, low power settling of a double-cascode telescopic opamp. A dynamic zero-crossing detector (ZCD) conserves power in the ZCBC by only creating high bandwidth in the ZCD near the zero-crossing instant. Measured results are presented from a pipelined A/D converter fabricated in 0.18 m CMOS. Using the Split-CLS structure, an opamp with 300 mV output swing is used to produce a pipeline stage output swing of 1.4 V. The proof-of-concept test chip achieves 68.3 dB SNDR (11.1b ENOB) and 76.3dB SFDR while sampling at 20 MHz, and consumes 17.2 mW at 1.8 V supply.},
keywords={CMOS integrated circuits;analogue-digital conversion;network synthesis;operational amplifiers;A/D converters;CMOS process;correlated level shifting;design;full signal swing;signal swing opamp;split-CLS pipelined ADC;zero-crossing based circuit;zero-crossing detector;Analog-digital conversion;Calibration;Capacitors;Switching circuits;Transistors;A/D;ADC;CBSC;CLS;Split-CLS;ZCBC;ZCD;comparator based switched capacitor circuit;correlated level shifting;dynamic zero crossing detector;pipelined analog-to-digital converter;scaled CMOS amplification technique;switched capacitor amplification;zero crossing based circuit},
doi={10.1109/JSSC.2010.2073190},
ISSN={0018-9200},
type={journal},}

2009

A multiplexer-based digital passive linear counter (PLINCO)
S. Weaver, B. Hershberg, P. K. Hanumolu, and U. Moon
In Electronics, Circuits, and Systems, 2009. ICECS 2009. 16th IEEE International Conference on, Dec, 2009.
»   [Paper]     [DOI]     [Abstract]     [Bibtex]

A passive linear counter (PLINCO) is presented. By cascading many passive transmission-gate multiplexers, a circuit is created that takes any scrambled unary-weighted digital input and sorts it into a thermometer coded output. Another variation produces a ¿one-hot¿ coded output. The number of muxes, n, required for these circuits increases with O{n2}, so a folding technique is presented that reduces the order to O{n log(n)}.
@INPROCEEDINGS{2009-icecs-plinco,
author={Weaver, S. and Hershberg, B. and Hanumolu, P.K. and Un-Ku Moon},
booktitle={{Electronics, Circuits, and Systems, 2009. ICECS 2009. 16th IEEE International Conference on}},
title={{A multiplexer-based digital passive linear counter (PLINCO)}},
year={2009},
month={Dec},
pages={607-610},
abstract={A passive linear counter (PLINCO) is presented. By cascading many passive transmission-gate multiplexers, a circuit is created that takes any scrambled unary-weighted digital input and sorts it into a thermometer coded output. Another variation produces a ¿one-hot¿ coded output. The number of muxes, n, required for these circuits increases with O{n2}, so a folding technique is presented that reduces the order to O{n log(n)}.},
keywords={analogue-digital conversion;comparators (circuits);counting circuits;multiplexing equipment;passive networks;PLINCO;comparators;flash analog-to-digital converters;folding technique;multiplexer-based digital passive linear counter;one-hot coded output;passive transmission-gate multiplexers;scrambled unary-weighted digital input;thermometer coded output;unary-weighted digital input;Adders;Analog-digital conversion;Clocks;Counting circuits;Error correction;Moon;Multiplexing;Resistors;Voltage;Wire},
doi={10.1109/ICECS.2009.5410852},
type={conference},}

2008

A 6b stochastic flash analog-to-digital converter without calibration or reference ladder
S. Weaver, B. Hershberg, D. Knierim, and U. Moon
In Solid-State Circuits Conference, 2008. A-SSCC '08. IEEE Asian, Nov, 2008.
»   [Paper]     [DOI]     [Abstract]     [Bibtex]

A 6-bit stochastic flash ADC is presented. By connecting many comparators in parallel, a reference ladder is avoided by allowing random offset to set individual trip points. The ADC transfer function is the cumulative density function of comparator offset. A technique is proposed to improve transfer function linearity by 8.5 dB. A test chip, fabricated in 0.18 mum CMOS, achieves ENOB over 4.9 b up to 18 MS/s with 900 mV supply and comparator offset standard deviation of 140 mV Comparators are digital cells to allow automated synthesis. Total core power consumption when fs = 8 MHz is 631muW.
@INPROCEEDINGS{2008-asscc-6b-stochastic-flash,
author={Weaver, S. and Hershberg, B. and Knierim, D. and Un-Ku Moon},
booktitle={{Solid-State Circuits Conference, 2008. A-SSCC '08. IEEE Asian}},
title={{A 6b stochastic flash analog-to-digital converter without calibration or reference ladder}},
year={2008},
month={Nov},
pages={373-376},
abstract={A 6-bit stochastic flash ADC is presented. By connecting many comparators in parallel, a reference ladder is avoided by allowing random offset to set individual trip points. The ADC transfer function is the cumulative density function of comparator offset. A technique is proposed to improve transfer function linearity by 8.5 dB. A test chip, fabricated in 0.18 mum CMOS, achieves ENOB over 4.9 b up to 18 MS/s with 900 mV supply and comparator offset standard deviation of 140 mV Comparators are digital cells to allow automated synthesis. Total core power consumption when fs = 8 MHz is 631muW.},
keywords={CMOS integrated circuits;analogue-digital conversion;comparators (circuits);flash memories;ADC transfer function;CMOS;ENOB;comparator offset;comparators;cumulative density function;size 0.18 mum;stochastic flash analog-to-digital converter;storage capacity 6 bit;voltage 900 mV;Analog-digital conversion;Ash;Calibration;Circuits;Gaussian distribution;Probability density function;Stochastic processes;Transfer functions;USA Councils;Voltage},
doi={10.1109/ASSCC.2008.4708805},
type={conference},}