Objective

Contribute meaningful advances to the fields of Integrated Circuit Design and Artificial Intelligence.

Experience

2013 – present      Principal Member of Technical Staff at imec

Leading research efforts in next-generation technologies for analog, mixed-signal, and RF integrated circuits with exposure to topics in ADCs, software defined radio, mmWave, emerging 5G technologies, IoT, and radar. The projects that I’ve been most heavily involved in span the entire wireless receiver chain, from the RF frontend down to the ADC, and are described on my projects page. I’ve worked extensively with 16nm FinFET, 28nm planar CMOS, and 180nm RF SOI technologies.

2006 – 2012      Graduate Student at Oregon State University

Conducted PhD research focused on scalable amplification solutions for switched capacitor circuits. Invented the the concept of ring amplification, which at ESSCIRC 2016 was listed as one of the key innovations in ADCs in the last decade, and continues to grow as a research topic. Designed and fabricated four pipelined ADCs, described on my projects page. All chips worked on the first attempt, and highlights include two consecutive state-of-the-art benchmarks for efficiency in high resolution ADCs. Followed advanced graduate courses in mixed-signal IC design, RF, filters, PLLs, delta-sigma, circuit simulators, and device physics. Advisor: Dr. Un-Ku Moon

2003 – 2012      Freelance Web Developer

Paid for living expenses and travel objectives during my college years by starting a web development service, working with clients including the IEEE Magnetics Society, DAMA International, and law firms in the Portland, Oregon area. Developed many custom web apps for clients, working mainly in html, css, php, and sql.

Publication

Papers

Full list of downloadable papers available on my publications page.
You can also find me on google scholar.

Selected publication:

Ring Amplifiers for Switched Capacitor Circuits
B. Hershberg, S. Weaver, K. Sobue, S. Takeuchi, K. Hamashita, and U. Moon
In Solid-State Circuits, IEEE Journal of, Dec, 2012.
»   [Paper]     [DOI]     [Abstract]     [Bibtex]

In this paper the fundamental concept of ring amplification is introduced and explored. Ring amplifiers enable efficient amplification in scaled environments, and possess the benefits of efficient slew-based charging, rapid stabilization, compression-immunity (inherent rail-to-rail output swing), and performance that scales with process technology. A basic operational theory is established, and the core benefits of this technique are identified. Measured results from two separate ring amplifier based pipelined ADCs are presented. The first prototype IC, a simple 10.5-bit, 61.5 dB SNDR pipelined ADC which uses only ring amplifiers, is used to demonstrate the core benefits. The second fabricated IC presented is a high-resolution pipelined ADC which employs the technique of Split-CLS to perform efficient, accurate amplification aided by ring amplifiers. The 15-bit ADC is implemented in a 0.18 μm CMOS technology and achieves 76.8 dB SNDR and 95.4 dB SFDR at 20 Msps while consuming 5.1 mW, achieving a FoM of 45 fJ/conversion-step.
@ARTICLE{2012-jssc-ringamp,
author={Hershberg, B. and Weaver, S. and Sobue, K. and Takeuchi, S. and Hamashita, K. and Un-Ku Moon},
journal={{Solid-State Circuits, IEEE Journal of}},
title={{Ring Amplifiers for Switched Capacitor Circuits}},
year={2012},
month={Dec},
volume={47},
number={12},
pages={2928-2942},
abstract={In this paper the fundamental concept of ring amplification is introduced and explored. Ring amplifiers enable efficient amplification in scaled environments, and possess the benefits of efficient slew-based charging, rapid stabilization, compression-immunity (inherent rail-to-rail output swing), and performance that scales with process technology. A basic operational theory is established, and the core benefits of this technique are identified. Measured results from two separate ring amplifier based pipelined ADCs are presented. The first prototype IC, a simple 10.5-bit, 61.5 dB SNDR pipelined ADC which uses only ring amplifiers, is used to demonstrate the core benefits. The second fabricated IC presented is a high-resolution pipelined ADC which employs the technique of Split-CLS to perform efficient, accurate amplification aided by ring amplifiers. The 15-bit ADC is implemented in a 0.18 μm CMOS technology and achieves 76.8 dB SNDR and 95.4 dB SFDR at 20 Msps while consuming 5.1 mW, achieving a FoM of 45 fJ/conversion-step.},
keywords={CMOS analogue integrated circuits;amplifiers;analogue-digital conversion;CMOS technology;SNDR pipelined ADC;Split-CLS;compression-immunity;power 5.1 mW;rapid stabilization;ring amplification;ring amplifier;size 0.18 micron;slew-based charging;switched capacitor circuit;word length 10.5 bit;word length 15 bit;Accuracy;CMOS integrated circuits;Gain;Inverters;Ring oscillators;Stability analysis;Transistors;A/D;ADC;CLS;RAMP;analog to digital conversion;analog to digital converter;correlated level shifting;high resolution;low power;nanoscale CMOS;rail-to-rail;ring amp;ring amplification;ring amplifier;ringamp;scalability;scaling;slew-based;split-CLS;stabilized ring oscillator;switched capacitor},
doi={10.1109/JSSC.2012.2217865},
ISSN={0018-9200},
type={journal},}

Academic Engagement

Regular peer reviewer for:

IEEE Journal of Solid State Circuits (JSSC)
IEEE Transactions on Circuits and Systems (TCAS)
IEEE Symposium on VLSI Technology and Circuits (VLSI)
IEEE Intl. Solid State Circuits Conference (ISSCC)
IEEE Electronic Letters
IEEE Transactions on VLSI Systems (TVLSI)

Patents

US 10484000 B2
US 10574255 B2
US 10536159 B2
US 10090852 B2
US 9948446
US 10230347 B2
US 9979376

+2 patents pending

Education

PhD, Electrical Engineering, 2012
BS Honors, Electrical Engineering, 2006
BS Honors, Computer Engineering, 2006
Minor, Computer Science, 2006

All degrees granted by
Oregon State University, Corvallis, USA

References

Available upon request.